1. Field of the Invention
The present invention relates to digital modulation circuit and method as well as digital demodulation circuit and method. More specifically, it relates to digital modulation circuit and method, digital demodulation circuit and method, circuit for and method of generating a demodulation carrier signal, and circuit for and method of generating a demodulation bit clock signal, which are well applicable to processing such as QPSK modulation/demodulation.
2. Description of Related Art
It is known that, for example, in a cable television (CATV) broadcast system or a satellite TV broadcast system, an image signal transmission method has been changed from an analog transmission to a digital transmission. In the digital transmission, a transmission side modulates an image signal into a digital signal and transmits it, and a reception side demodulates the received digital signal into the image signal.
As digital modulation, for example, quadrature phase shift keying (QPSK) modulation is known. FIG. 1 shows a configuration of one example of a conventional QPSK modulation circuit.
This QPSK modulation circuit 210 has an input terminal 211 for receiving an I signal as a first-channel digital signal, an input terminal 212 for receiving a Q signal as a second-channel digital signal, and an input terminal 213 for receiving a bit clock signal BCK having a frequency corresponding to a bit rate of the I signal or the Q signal.
Further, the QPSK modulation circuit 210 has a D flip-flop 214 for synchronizing each bit data consisting of the I signal received by the input terminal 211 with the bit clock signal BCK and a D flip-flop 215 for synchronizing each bit data consisting of the Q signal received by the input terminal 212 with the clock signal BCK.
It is to be noted that to data terminals D of the D flip-flops 214 and 215, the I signal and the Q signal received by the input terminals 211 and 212 are applied, respectively. Further, to clock signal terminals CK of the D flip-flops 214 and 215, the bit clock signal BCK received by the input terminal 213 is applied.
Further, the QPSK modulation circuit 210 has a low-pass filter 216 for limiting a frequency band in order to remove an unnecessary high-frequency-band signal from the I signal output from the D flip-flop 214 and a low-pass filter 217 for limiting a frequency band in order to remove an unnecessary high-frequency-band signal from the Q signal output from the D flip-flop 215.
Further, the QPSK modulation circuit 210 has an oscillator 218 for generating a carrier signal Sc, an amplifier 219 for amplifying the carrier signal Sc generated by this oscillator 218, and a π/4 radian phase shifter 221 and a −π/4 radian phase shifter 222 for shifting a phase of the carrier signal Sc amplified by this amplifier 219 by 45 degrees (π/4) and −45 degrees (−π/4) to obtain first and second carrier signals Sc1 and Sc2, respectively. In this case, the first carrier signal Sc1 and the second carrier signal Sc2 have a phase difference of 90 degrees with respect to each other.
Further, the QPSK modulation circuit 210 has a mixer circuit 223 as accumulation means for accumulating the I signal, which is band-limited through the low-pass filter 216, and the carrier signal Sc1 generated by the π/4 radian phase shifter 221. The QPSK modulation circuit 210 has a mixer circuit 224 as accumulation means for accumulating the Q signal, which is band-limited through the low-pass filter 217, and the carrier signal Sc2 generated by the −π/4 radian phase shifter 222. These mixer circuits 223 and 224 each constitute a two-phase shift keying modulation circuit.
Further, the QPSK modulation circuit 210 has an adder 225 for adding up output signals of the mixer circuits 223 and 224 to obtain a modulated QPSK signal SQM as a modulated quadrature signal and an output terminal 226 for outputting this modulated QPSK signal SQM.
The following will describe operations of the QPSK modulation circuit 210 shown in FIG. 1.
The I signal (first-channel digital signal) input to the input terminal 211 is applied to the data terminal D of the D flip-flop 214. The Q signal (second-channel digital signal) input to the input terminal 212, on the other hand, is applied to the data terminal D of the D flip-flop 215. To the clock signal terminals CK of these D flip-flops 214 and 215, the bit clock signal BCK from the input terminal 213 is input.
The D flip-flops 214 and 215 sequentially latch items of bit data of the respective I and Q signals using the bit clock signal BCK respectively. That is, in the D flip-flops 214 and 215, the items of bit data of the respective I and Q signals are synchronized with the bit clock signal BCK.
The I signal and the Q signal output from the respective D flip-flops 214 and 215 are band-limited in the low-pass filters 216 and 217 to remove their unnecessary high-frequency-band signals and then they are input into the mixer circuits 223 and 224, respectively. FIG. 2A shows a frequency spectrum of each of the I signal and the Q signal before they are band-limited by the low-pass filters 216 and 217. FIG. 2B shows a frequency spectrum of each of the I signal and the Q signal after they are band-limited by the low-pass filters 216 and 217. Letters, fS indicate a bit clock signal frequency, which is a frequency of the bit clock signal BCK.
Further, the carrier signal Sc generated by the oscillator 218 is amplified by the amplifier 219 and then input to the phase shifters 221 and 222. In these phase shifters 221 and 222, the carrier signal Sc has its phase shifted by 45 and −45 degrees to provide the carrier signals Sc1 and Sc2 having a phase difference of 90 degrees with respect to each other.
The carrier signal Sc1 obtained at the phase shifter 221 is input to the mixer circuit 223. This mixer circuit 223 accumulates the I signal band-limited by the low-pass filter 216 and the carrier signal Sc1, to perform two-phase shift keying modulation. The carrier signal Sc2 obtained at the phase shifter 222, on the other hand, is input to the mixer circuit 224. This mixer circuit 224 accumulates the Q signal band-limited by the low-pass filter 217 and the carrier signal Sc2, to perform two-phase shift keying modulation.
Output signals of the mixer circuits 223 and 224 are input to the adder 225 where they are added up. From this adder 225, the modulated QPSK signal SQM as a modulated quadrature signal is obtained and output to the output terminal 226. FIG. 2C shows a frequency spectrum of the modulated QPSK signal SQM output to the output terminal 226. In the figure, letters, f0 indicates a frequency of the carrier signals Sc1 and Sc2.
The following will describe a QPSK demodulation circuit for obtaining the I signal and the Q signal by demodulating the modulated QPSK signal SQM obtained at the QPSK modulation circuit 210 shown in FIG. 1. FIG. 3 shows a configuration of one example of the conventional QPSK demodulation circuit.
This QPSK demodulation circuit 250 has an input terminal 251 receives the modulated QPSK signal SQM and a band-pass filter 252, for removing an unnecessary frequency component from the modulated QPSK signal SQM received by this input terminal 251. This band-pass filter 252 extracts a frequency component in a band of f0−fS through f0+fS (see FIG. 2C).
Further, the QPSK demodulation circuit 250 has a voltage-controlled oscillator (VCO) 253 for generating the carrier signal Sc, an amplifier 254 for amplifying the carrier signal Sc generated by this oscillator 253, and a π/4 radian phase shifter 261 and a −π/4 radian phase shifter 262 for shifting the phase of the carrier signal Sc amplified by this amplifier 254 by 45 degrees (π/4) and −45 degrees (−π/4) to obtain the first and second carrier signals Sc1 and Sc2, respectively. In this case, the first carrier signal Sc1 and the second carrier signal Sc2 have a phase difference of 90 degrees with respect to each other.
Further, the QPSK demodulation circuit 250 has mixer circuits 263 and 264 each constituting a phase detection circuit. The mixer circuit 263 accumulates the modulated QPSK signal SQM whose unnecessary frequency component has been removed through the band-pass filter 252 and the carrier z signal Sc1 generated by the π/4 radian phase shifter 261 to perform phase detection, thus obtaining a detected first-channel output. The mixer circuit 264, on the other hand, accumulates the modulated QPSK signal SQM whose unnecessary frequency component has been removed through the band-pass filter 252 and the carrier signal Sc2 generated by the −π/4 radian phase shifter 262 to perform phase detection, thus obtaining a detected second-channel output.
Further, the QPSK demodulation circuit 250 has a low-pass filter 265 for limiting a band of a detected output obtained by the mixer circuit 263 to thereby shape its waveform and a low-pass filter 266 for limiting a band of a detected output obtained by the mixer circuit 264 to thereby shape its waveform.
Further, the QPSK demodulation circuit 250 has a bit clock signal reproduction circuit 267. This bit clock signal reproduction circuit 267 obtains from a detected second-channel output whose waveform has been shaped by the low-pass filter 266 a frequency component corresponding to a bit rate of this output, thereby reproducing the bit clock signal BCK. It is to be noted that this bit clock signal reproduction circuit 267 can reproduce the bit clock signal BCK similarly even by using a detected first-channel output whose waveform has been shaped by the low-pass filter 265.
Further, the QPSK demodulation circuit 250 has a D flip-flop 271 for extracting each bit data of the I signal, which is a first-channel digital signal, from a detected output whose band has been limited by the low-pass filter 265. The QPSK demodulation circuit 250 also has a D flip-flop 272 for extracting each bit data of the Q signal, which is a second-channel digital signal, from a detected output whose band has been limited by the low-pass filter 266. The QPSK demodulation circuit 250 further has output terminals 273 and 274 for outputting the bit data extracted by these D flip-flops 271 and 272, as the I signal and the Q signal, respectively.
Further, the QPSK demodulation circuit 250 has mixer circuits 281 and 282, an adder 283, and a low-pass filter 284, each of which constitutes a carrier signal reproduction circuit together with the above-mentioned voltage-controlled oscillator 253.
The mixer circuit 281 accumulates detected outputs whose bands have been limited by the low-pass filters 265 and 266, respectively. The mixer circuit 282 also accumulates detected outputs whose bands have been limited by the low-pass filters 265 and 266, respectively. The adder 283 adds up output signals of the mixer circuits 281 and 282. The low-pass filter 284 limits a band of an added-up signal obtained at the adder 283 to thereby extract a control voltage CNT to be input to the voltage-controlled oscillator 253. By controlling an oscillated frequency of the voltage-controlled oscillator 253 by using the above-mentioned control voltage CNT, a frequency of the carrier signal Sc generated by the voltage-controlled oscillator 253 corresponds to a carrier signal frequency of the modulated QPSK signal SQM to be input to the input terminal 251.
The following will describe operations of the QPSK demodulation circuit 250 shown in FIG. 3.
The modulated QPSK signal SQM received by the input terminal 251 has its unnecessary frequency component removed by the band-pass filter 252 and is then input to the mixer circuits 263 and 264. The amplifier 254 amplifies a carrier signal Sc generated by the voltage-controlled oscillator 253. The carrier signal Sc thus amplified is input to the phase shifters 261 and 262. At these phase shifters 261 and 262, the carrier signal Sc has its phase shifted by 45 degrees and −45 degrees to provide carrier signals Sc1 and Sc2, respectively, having a phase difference of 90 degrees with respect to each other.
The carrier signal Sc1 obtained at the phase shifter 261 is input to the mixer circuit 263. At this mixer circuit 263, the modulated QPSK signal SQM whose unnecessary frequency component has been removed by the band-pass filter 252 and the carrier signal Sc1 are accumulated to perform phase detection, thereby obtaining a detected first-channel output.
Similarly, the carrier signal Sc2 obtained at the phase shifter 262 is input to the mixer circuit 264. At this mixer circuit 264, the modulated QPSK signal SQM whose unnecessary frequency component has been removed by the band-pass filter 252 and the carrier signal Sc2 are accumulated to perform phase detection, thereby obtaining a detected second-channel output.
The detected outputs obtained at these mixer circuits 263 and 264 have their bands limited by the low-pass filters 265 and 266 and are then input to the data terminals D of the D flip-flops 271 and 272, respectively. The clock signal terminals CK of these D flip-flops 271 and 272 are each supplied with the bit clock signal BCK reproduced by the bit clock signal reproduction circuit 267 based on the detected output whose band has been limited by the low-pass filter 266.
The D flip-flops 271 and 272 latch the detected first-channel and second-channel outputs whose bands have been limited by the low-pass filters 265 and 266, respectively, using the bit clock signal BCK, thereby sequentially extracting items of bit data consisting of the respective I signal (first-channel digital signal) and the Q signal (second-channel digital signal). The items of bit data extracted at these D flip-flops 271 and 272 are output to the output terminals 273 and 274 as the I signal and the Q signal, respectively.
Further, the detected first-channel and second-channel outputs whose bands have been limited by the low-pass filters 265 and 266 respectively are input to the mixer circuit 281 as well as to the mixer circuit 282. At the mixer circuits 281 and 282, each of the detected first-channel output and the second-channel output is accumulated.
Output signals of these mixer circuits 281 and 282 are added up at the adder 283, whose output has its band limited at the low-pass filter 284 and is input as the control voltage CNT to the voltage-controlled oscillator 253. Accordingly, the frequency of the carrier signal Sc generated by the voltage-controlled oscillator 253 corresponds to the carrier signal frequency of the modulated QPSK signal SQM input to the input terminal 251, so that as described above the I signal and the Q signal can be obtained well by demodulating the modulated QPSK signal SQM.
The modulated QPSK signal SQM obtained by the QPSK modulation circuit 210 shown in FIG. 1 contains no carrier signal components, so that the QPSK demodulation circuit 250 shown in FIG. 3 for demodulating this modulated QPSK signal SQM is provided with a carrier signal generation circuit which is constituted of the mixer circuits 281 and 282, the adder 283, the low-pass filter 284, and the voltage-controlled oscillator 253.
This carrier signal generation circuit, however, may in principle generate a pseudo-demodulation carrier signal, which leads to malfunctioning. Further, if this carrier signal generation circuit is used, the number of the mixer circuits used in the demodulation circuit 250 increases, thus complicating a circuit configuration. Furthermore, if the frequency of the carrier signal is high, delays in the circuit elements prevent the carrier signal from being reproduced, thereby disabling the demodulation.
It is an object of the present invention to stably obtain a demodulation carrier signal and a demodulation bit clock signal with a simple configuration and without difficulty when demodulating a modulated digital signal, for example, a modulated QPSK signal.